1. Technical Field to which the Invention Belongs
The present invention relates to an art making it possible to achieve complete compatibility with a non-defective semiconductor memory by combining semiconductor memories having irremediable local defects, particularly to an art for constituting a memory device or a memory card by combining a plurality of flash memories having irremediable defects which can be apparently ignored.
2. Technical Background of the Invention
When some of the memory cells in a semiconductor memory are defective, it is possible to repair the semiconductor memory by replacing the defective memory cells with redundant memory cells. However, when a malfunctioning portion of a semiconductor memory exceeds a remediable range, the semiconductor memory is regarded as defective. A semiconductor memory having no malfunctioning portion or whose malfunctioning portion is in a remediable range is referred to as a complete composite conforming circuit. The defective product can be used as an operable product by removing defective portions from the memory and decreasing the entire memory capacity of the memory to xc2xd or xc2xc. This locally operable product is a partial product. Partial products can be used by mutually combining partial products in which the operable portion of one partial product compensates the inoperable portion of the other product. For example, in the case of a low-order partial product, in which the high-order half of the memory area is defective, and a high-order partial product, in which the low-order half of the memory area is defective, it is possible to use these partial products in combination by fixing the address input terminal of an address bit provided to select the high order or low order portion of the memory area to the selection level of a low-order side memory area at the outside, in the case of the low-order partial product, and fixing the address input terminal of an address bit provided to select the high order or low order portion of the memory area at the outside in the case of a high-order partial product.
When the data input/output terminals of the high-order partial product and low-order partial product are connected to each other in common at the outside to use the partial products instead of a non-defective product, chip selection must be performed for each partial product by using different chip selection signals. Therefore, to use a partial product for a semiconductor memory in a memory card, it is necessary to increase the number of chip selection signals compared to the case where a non-defective product is used, and moreover, it is necessary to use a decoder having different logic for chip selection when using a partial product in comparison to that a non-defective product.
Moreover, each defective portion of a plurality of partial products may have a difference depending on the fabrication process. When combining a plurality of partial products in which defective-portion tail address regions are complementary instead of using a non-defective product, if the partial products having different defective portions are biased in quantity, a larger portion of the partial products are left unused.
Furthermore, in the case of a nonvolatile semiconductor memory, such as a flash memory, rewriting of information is performed by bringing the memory cells into an erasing state and then data write is performed. Also, a verify operation is necessary for the erase and write operations. In the case of a semiconductor memory, such as a flash memory, erase, erase verify, write, and write verify operations are controlled inside the memory so that data can be written even on the system (on-board state). The state in which a rewrite operation is performed inside is reported to an access body, such as a microprocessor, in accordance with, for example, a ready/busy signal. When a failure occurs in the erase operation or write operation due to deterioration of the characteristics of a memory cell, an erase state or write state necessary for the memory cell cannot be obtained even if the erase and erase verify operations and write and write verify operations are repeated many times and the internal rewrite control operation is abnormally ended.
It is an object of the present invention to provide a semiconductor memory which directly applicable to a memory device and a memory card by using a plurality of partial products instead of a non-defective product or complete composite conforming circuit.
It is another object of the present invention to provide a semiconductor memory which is capable of preventing a contradiction of the internal states from occurring between a partial product in which the operation of its defective portion is designated by an access from an external unit and another partial product substituted for the former partial product, and, moreover, to provide a memory device using the memory.
It is still another object of the present invention to provide a semiconductor memory which is capable of changing the address arrangement of an operable portion separated from a defective portion irrespective of built-in address decoding logic, and, moreover, to provide a memory device using the memory.
It is still another object of the present invention to provide a memory card which is capable of using an address decoding logic for chip selection for a semiconductor memory in common with a case where a complete composite conforming circuit is used even when a partial product is used.
The above and other objects and novel features of the present invention will become more apparent from the description provided in this specification and the accompanying drawings.
Semiconductor memories (1, 1C) of the present invention include a plurality of memory blocks (2, 3 or 2Y, 3Y) constituted by a plurality of memory cells, a data input/output buffer (7) to which data to be written in the memory blocks is supplied and which outputs the data read out of the memory blocks to an external unit, and first control means for controlling the rewriting of data into and the reading of data from the memory cells. The first control means is denoted by symbol 11 in FIG. 1 and by symbols 43Y, 45, and 46Y in FIG. 31. The semiconductor memories are provided with first storage means (30, 47) for designating defective memory blocks included in the above memory blocks and detection means (32, 48Y) for detecting the access to the defective memory blocks designated by the first storage means in accordance with an address signal. In this case, when the detection means detects an access to the defective memory blocks, the control means inhibits a data rewrite operation in the case of a data rewrite operation and inhibits a data output operation of the data input/output buffer in the case of a data read operation.
Moreover, semiconductor memories (1, 1B, or 1C) according to another aspect of the present invention include a plurality of memory blocks (2, 3 or 2Y, 3Y) constituted by a plurality of electrically erasable memory cells, a data input/output buffer (7) to which data to be written in the memory blocks is supplied from an external unit and which outputs data read out of the memory blocks to an external unit, and first control means for controlling the writing of data into and the reading of data from the memory cells. The first control means is denoted by symbol 11 in FIG. 1, and by symbols 43, 44, 45, and 46 in FIG. 15 and by symbols 43Y, 45, and 46 in FIG. 31. The semiconductor memories are provided with first storage means (30, 47) for designating defective memory blocks included in the above memory blocks and detection means (32, 48, 48Y) for detecting an access to the defective memory blocks designated by the first storage means in accordance with an address signal. The control means is set to a status (MR/B) representing the completion of the data rewrite operation in the case of a data rewrite operation when the detection means detects an access to the defective memory blocks so that the status can be output to an external unit irrespective of the completion of the data rewrite operation, and the control means is set to inhibit a data output operation of the data input/output buffer in the case of a data read operation.
A semiconductor memory according to still another aspect of the present invention includes a plurality of memory blocks (72, 73) constituted by a plurality of memory cells, data input/output buffers (77L, 77U) to which data to be written in the memory blocks is supplied from an external unit and which outputs data read out of the memory blocks to an external unit, and first control means for controlling the writing of data into and the reading of data from the memory cells, the first control means having first storage means (100) for designating defective memory blocks included in the above memory blocks. In this case, the control means inhibits a data rewrite operation for the defective memory blocks designated by the first storage means in the case of a data rewrite operation and inhibits the data output operation of the data input/output buffer in the case of a data read operation.
It is possible to use the least significant bit (A0) or the most significant bit (A20) of an address signal for the address information for designating a defective memory block.
To realize an arrangement of the addresses of defective memory blocks on a semiconductor memory, it is possible to provide logic means (104) for selectively inverting the inputs so that the inputs can be output and second storage means (34) for storing control information for determining the propriety of the input inverting operation by the logic means for a path for supplying address information to the detection means in order to detect an access to the defective memory blocks designated by the first storage means.
By using the above semiconductor memories as partial products, it is possible to realize a compatible product having the same memory capacity as that of a semiconductor memory of a complete composite conforming circuit using a memory device (40) which includes the semiconductor memories (1-L, 1-U) having the relation that one semiconductor memory is substituted for the defective memory block of the other semiconductor memory and vice versa, and in which an external terminal having the same function is connected between the semiconductor memories in common.
A memory card (50) using the memory devices is constituted by mounting a plurality of memory devices on a card substrate. Each memory device is provided with an external-data input/output terminal, a chip selection terminal and an address input terminal, all serving as the above external terminals, in which the chip selection terminal is connected to chip-selection signal wirings different from each other on the card substrate and external address input terminals of the memory devices are connected to address signal wirings of the card substrate in common, for every memory device in which the external-data input/output terminal is connected to the data wiring on the card substrate in common.
The memory card is provided with a card controller (52), having one end which is interfaced with the outside of the card substrate and another end which is connected to the data wiring, chip selection signal wirings and address signal wirings, and the card controller can be constituted by including decoding means (54) for decoding part of the address information supplied from an external unit to generate the chip selection signal.
According to the above-described means, when a memory block selected in accordance with the address information supplied from an external unit coincides with a memory block (defective memory block in a partial product) designated by the first storage means, a data rewrite operation is inhibited by the first control means in the case of a data rewrite operation, and a data output operation of the data input/output buffer is inhibited by the first control means in the case of a data read operation. By means of another aspect, when access to a defective memory block is detected, a status representing the completion of the data rewrite operation is set up so that it can be output to an external unit by the first control means irrespective of the completion of the operation in the case of a data rewrite operation, and a data output operation of the data input/output buffer is inhibited by the first control means in the case of a data read operation.
The inhibiting of a semiconductor memory used as a partial product makes it possible to use a partial product without requiring the processing of fixing a specific address for designating a memory block outside the semiconductor memory on a system. For example, when the above semiconductor memory is provided with two memory blocks, by combining a semiconductor memory (1-U) used as a high-order partial product and a semiconductor memory (1-L) used as a low-order partial product to form a memory device (40) by connecting its external terminals in common, the memory device (40) achieves the compatibility of a semiconductor memory having a complete composite conforming circuit from the viewpoint of external terminal specification or utilization mode.
In the case of a semiconductor memory, such as a flash memory, which independently performs the processing of responding to a command supplied from an external unit, even if an instruction to execute the information rewrite operation is given from an external unit to a defective memory block in a partial product, the information rewrite operation of the memory block is inhibited or a status representing the completion of the data rewrite operation is set up so that it can be output to the external unit irrespective of the completion of the operation as described above. Therefore, when an instruction to execute the operation of a defective portion of a partial product is given by an access from an external unit, it is possible to prevent contradiction from occurring in the internal state between the partial product and another partial product substituted for the defective portion of the former partial product.
It is considered that defective portions of a plurality of partial products are biased depending on the fabrication process. By using the logic means for selectively logic-inverting address information provided to select a memory block in accordance with a value preset in the second storage means, it is possible to optionally change the arrangement of memory blocks apparently operable with respect to an address signal supplied from an external unit depending on the type of setting information provided by the second storage means even if partial products whose defective portions are different from each other are biased in quantity. Thereby, when substituting partial products whose operational regions are complementary for a non-defective product by combining them, it is possible to prevent defective partial products of one defect type more than the other defect type in quantity to be left unused.
For example, when a flash memory is used as a semiconductor memory and the semiconductor memory is provided with two memory blocks, it is possible to mount a semiconductor memory used as a high-order partial product and a semiconductor memory used as a low-order partial product on a memory card using the partial product of the semiconductor memory provided with two memory blocks by substituting the high-order and low-order partial products for a complete composite conforming circuit and connecting the external terminals thereof in common on a wiring board. Because the processing for the defective portion of a semiconductor memory used as a partial product is realized in the semiconductor memory, the processing for fixing a specific address terminal of the semiconductor memory is not required at all. Even if a semiconductor memory used in a memory card is a partial product, it is possible to use in common the wiring of a mounting board and the logic of a card controller, particularly the logic of a chip selecting decoder of a semiconductor memory.
Thus, the present invention makes it possible to realize a good compatibility between a memory device or memory card using a partial product and a device or memory card using a complete composite conforming circuit. It is possible to directly employ a partial product of a semiconductor memory for a memory device or memory card in place of a complete composite conforming circuit.